3D Non-Volatile Memory With Metal Silicide Interconnect

摘要

A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.

主权项

1. A peripheral area of a 3D stacked non-volatile memory device, comprising:
a substrate; a stack of alternating undoped/lightly doped and heavily doped polysilicon layers on the substrate in at least one peripheral area of the substrate, lateral of at least one cell area of the substrate, the alternating undoped/lightly doped and heavily doped polysilicon layers extend upward from a bottom layer of heavily doped polysilicon and include at least one other layer of heavily doped polysilicon, the at least one peripheral area does not comprise vertical columns of NAND cells; at least one below-stack metal layer carried by the substrate, below the stack; at least one contact structure of the at least one lower metal layer, extending up to the bottom layer of heavily doped polysilicon; at least one above-stack metal layer, above the stack; at least one contact structure extending from the bottom layer of heavily doped polysilicon to the at least one above-stack metal layer; and at least one contact structure extending from the at least one other layer of heavily doped polysilicon to the at least one above-stack metal layer, the bottom layer of heavily doped polysilicon is connected in parallel with the at least one other layer of heavily doped polysilicon to the at least one above-stack metal layer by the at least one contact structure extending from the bottom layer of heavily doped polysilicon to the at least one above-stack metal layer and the at least one contact structure extending from the at least one other layer of heavily doped polysilicon to the at least one above-stack metal layer.