发明名称 RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN
摘要 <p>A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.</p>
申请公布号 WO2015027023(A1) 申请公布日期 2015.02.26
申请号 WO2014US52017 申请日期 2014.08.21
申请人 QUALCOMM INCORPORATED 发明人 GULATI, CHIRAG;CHABA, RITU;HOLLA VAKWADI, LAKSHMIKANTHA
分类号 G01R31/3185;G11C29/32 主分类号 G01R31/3185
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