INTER-CORE COOPERATIVE TLB PREFETCHERS

摘要

A chip multiprocessor includes a plurality of cores each having a translation lookaside buffer (TLB) and a prefetch buffer (PB). Each core is configured to determine a TLB miss on the core's TLB for a virtual page address and determine whether or not there is a PB hit on a PB entry in the PB for the virtual page address. If it is determined that there is a PB hit, the PB entry is added to the TLB. If it is determined that there is not a PB hit, the virtual page address is used to perform a page walk to determine a translation entry, the translation entry is added to the TLB and the translation entry is prefetched to each other one of the plurality of cores.

主权项

1. A chip multiprocessor comprising:
at least one prefetch buffer (PB); and a plurality of cores each communicatively coupled to the at least one prefetch buffer and comprising a translation lookaside buffer (TLB), wherein each of the plurality of cores is adapted to:
determine a TLB miss on the TLB for a virtual page address;determine whether or not there is a PB hit on a PB entry in the at least one PB for the virtual page address;if it is determined that there is a PB hit:
add the PB entry to the TLB; andif it is determined that the PB entry was prefetched from another of the plurality of cores, send a request to the other of the plurality of cores from which the PB entry was prefetched requesting an increase in a value of a confidence counter associated with the core;if it is determined that there is not a PB hit:
use the virtual page address to perform a page walk to determine a translation entry;add the translation entry to the TLB;prefetch the translation entry to each of the other plurality of cores each associated with a confidence counter value greater than or equal to a predetermined amount;send a request to increase a value of a confidence counter associated with the core; andsend a request to decrease a value of a confidence counter on the occurrence of a PB entry eviction.