Semiconductor Device Having Multi-Level Wiring Structure

摘要

Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.

主权项

1. A semiconductor device comprising:
a memory mat including a plurality of memory cells; a sense amplifier located in a sense amplifier area and amplifying data supplied from the memory cells to generate first amplified data; a main amplifier that amplifies the first amplified data supplied from the sense amplifier; a main I/O line extends in a first direction to connect the sense amplifier to the main amplifier, the main I/O line including a first section provided over the memory mat as a first wiring layer and the second section provided over the sense amplifier area as a third wiring layer different from the first wiring layer; a power-supply line provided as the third wiring layer such that the power-supply line overlaps with the first section of the main I/O line; a sub-word line extending in a second direction, which is crossing to the first direction, and being connected to the plurality of memory cells; a sub-word driver driving a corresponding one of the sub-word lines and placed between the memory mats; and a main word line extending in the second direction and being connected to the sub-word driver.