| 发明名称 |
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION |
| 摘要 |
A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level. |
| 申请公布号 |
US2015054567(A1) |
申请公布日期 |
2015.02.26 |
| 申请号 |
US201313975074 |
申请日期 |
2013.08.23 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
RASOULI Seid Hadi;DATTA Animesh;KWON Ohsang |
| 分类号 |
H01L27/092;H03K17/687;H03K17/16;H01L21/8238 |
主分类号 |
H01L27/092 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A complementary metal oxide semiconductor (CMOS) device including a plurality of p-type metal oxide semiconductor (PMOS) transistors each having a PMOS drain and a plurality of n-type metal oxide semiconductor (NMOS) transistors each having an NMOS drain, comprising:
a first interconnect on an interconnect level connecting a first subset of the PMOS drains together; a second interconnect on the interconnect level connecting a second subset of the PMOS drains together, the second subset of the PMOS drains being different than the first subset of the PMOS drains, the first interconnect and the second interconnect being disconnected on the interconnect level; a third interconnect on the interconnect level connecting a first subset of the NMOS drains together; and a fourth interconnect on the interconnect level connecting a second subset of the NMOS drains together, the second subset of the NMOS drains being different than the first subset of the NMOS drains, the third interconnect and the fourth interconnect being disconnected on the interconnect level, wherein the first interconnect, the second interconnect, the third interconnect, and the fourth interconnect are coupled together though at least one other interconnect level. |
| 地址 |
San Diego CA US |
