VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY

摘要

A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.

主权项

1. A semiconductor device, comprising:
a drain contact; a plurality of nanopillars directly connected to said drain contact, wherein each of said plurality of nanopillars comprises a channel of said semiconductor device, wherein each of said plurality of channels comprises undoped III-V semiconductor material; a gate dielectric layer surrounding said plurality of nanopillars; a gate contact connected to a gate metal layer which is connected to said gate dielectric layer; a substrate connected to said plurality of nanopillars via a first layer of doped III-V semiconductor material, wherein said gate metal layer is isolated from said first layer of doped III-V semiconductor material by said gate dielectric layer; and a source contact directly connected to said substrate.