| 发明名称 |
BIMODAL FUNCTIONALITY BETWEEN COHERENT LINK AND MEMORY EXPANSION |
| 摘要 |
Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed. |
| 申请公布号 |
US2015058524(A1) |
申请公布日期 |
2015.02.26 |
| 申请号 |
US201213808314 |
申请日期 |
2012.01.04 |
| 申请人 |
Creta Kenneth C.;Horihan Jason W.;Blankenship Robert G.;Cheng Kai |
发明人 |
Creta Kenneth C.;Horihan Jason W.;Blankenship Robert G.;Cheng Kai |
| 分类号 |
G06F3/06;G11C13/00;G11C14/00 |
主分类号 |
G06F3/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
a first interface to couple the processor to one or more agents via a coherent interconnect; and logic to couple the processor to one or more Dual Inline Memory Modules (DIMMs), wherein the logic is to support read or write commands directed at the one or more DIMMs based on a value of a single bit. |
| 地址 |
Gig Harbor WA US |
