DIGITAL RECEIVER AND METHOD FOR DEMODULATING PULSE-WIDTH MODULATED SIGNALS

摘要

The present invention provides a digital receiver configured to demodulate or decode a pulse-width modulated (PWM) signal from a transmitter. The receiver digitally demodulates or decodes the pulse-width modulated signal so as to obtain (binary) values of data modulated on pulse periods of the pulse-width modulated signal. The digital receiver includes multiple delay cells coupled to one another in series and a sampling circuit coupled to one of the delay cells. A sequential coupling of the delay cells composes a signal path, and each of the delay cells is designed to provide a corresponding delay to a corresponding input signal propagating along the signal path so as to generate a delayed signal as its output.

主权项

1. A receiver configured to demodulate a pulse-width modulated (PWM) signal, comprising:
multiple first delay cells coupled to one another in series in a first signal path, wherein said multiple first delay cells are operable to propagate a first signal along said first signal path for duration of a first interval between a first logic-level transition of said PWM signal and a second logic-level transition of said PWM signal; and multiple second delay cells coupled to one another in series in a second signal path, wherein said multiple second delay cells are operable to propagate said first signal along said second signal path for duration of a second interval between said second logic-level transition of said PWM signal and a third logic-level transition of said PWM signal, wherein said second logic-level transition is between said first and third logic-level transitions and is followed by said third logic-level transition, wherein an interval between said first and third logic-level transitions represents a pulse period of said PWM signal, wherein each of said multiple first and second delay cells is operable to delay said first signal input to said each of said multiple first and second delay cells for a period of time as its output, wherein said first signal propagating along said second signal path is configured to change a logic level at said output of one of said multiple second delay cells.