FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF

摘要

A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a command receiver, a command decoder and a core circuit. The command receiver sequentially receives a plurality of command data through the data input pin and the clock pin. The command decoder receives a command sequence formed by the command data, and compares the command sequence with a reference sequence to generate a reset signal. The core circuit receives the reset signal to activate a reset operation according to the reset signal.

主权项

1. A flash memory apparatus with a serial interface, comprising:
a command receiver, coupled to a clock pin and a data input pin of the flash memory apparatus, and sequentially receiving a plurality of command data through the data input pin and the clock pin; a command decoder, coupled to the command receiver, receiving a command sequence formed by the command data, and comparing the command sequence with a reference sequence to generate a reset signal; and a core circuit, coupled to the command decoder, for receiving the reset signal to activate a reset operation according to the reset signal.