| 摘要 |
According to one embodiment, a resistance change memory includes a first memory cell, a word line, a first bit line, first and second inverters, first to sixth MOS transistors, and a control circuit. The first transistor is connected to the first output terminal of the first inverter. The second transistor is connected to the second output terminal of the second inverter. The fifth transistor has a first current path whose one end is connected to the first voltage terminal of the first inverter. The sixth transistor has a second current path whose one end is connected to the third voltage terminal of the second inverter. The control circuit makes the first and second transistors a cutoff state by a first signal and makes the fifth and sixth transistors the cutoff state by a second signal in a standby state. |
| 主权项 |
1. A resistance change memory comprising:
a first memory cell including a resistance change element; a word line connected to the first memory cell and driven based on an address signal; a first bit line connected to the first memory cell, crossing the word line, and selected based on the address signal; a first inverter including a first input terminal, a first output terminal, and first and second voltage terminals; a second inverter including a second input terminal, a second output terminal, and third and fourth voltage terminals, wherein the second input terminal is connected to the first output terminal and the second output terminal is connected to the first input terminal; a first MOS transistor connected to the first output terminal, wherein a first signal is supplied to a gate of the first MOS transistor; a second MOS transistor connected to the second output terminal, wherein the first signal is supplied to a gate of the second MOS transistor; a third MOS transistor connected to the first voltage terminal; a fourth MOS transistor connected to the third voltage terminal; a fifth MOS transistor having a first current path whose one end is connected to the first voltage terminal, wherein a current flowing to the first bit line is supplied to the other end of the first current path and a second signal is supplied to a gate of the fifth MOS transistor; a sixth MOS transistor having a second current path whose one end is connected to the third voltage terminal, wherein a reference current is supplied to the other end of the second current path and the second signal is supplied to a gate of the sixth MOS transistor; and a control circuit generating the first and second signals, wherein the control circuit makes the first and second MOS transistors a cutoff state by the first signal and makes the fifth and sixth MOS transistors the cutoff state by the second signal in a standby state. |
