| 摘要 |
<p>The present invention relates to a static random access memory. The static random access memory includes: a memory cell array; a control logic which generates first and second write clock signals with a pulse width shorter than that of a clock signal in response to the clock signal; a row decoder which does or does not select word lines during a write operation in response to the second write clock signal; a column selection unit which does or does not select the bit lines and the reverse bit lines; a sensing amplifier which senses the status of the bit lines and the reverse bit lines selected during a read operation; and a write driver which bias the selected lines and the reverse bit lines in response to a first write clock signal during the write operation.</p> |
