| 摘要 |
1,053,442. Semi-conductor devices. MOTOROLA Inc. May 10, 1965 [May 18, 1964], No. 19651/65. Heading H1K. A field effect transistor is produced in a wafer comprising an N-type silicon layer 34<SP>1</SP> epitaxially deposited on a P-type silicon substrate 40, Fig. 4B (not shown), by oxidizing both major faces and selectively etching the oxide layer on the N-type surface to leave a circular region of oxide, Fig. 4D (not shown). Boron is diffused into the wafer to form P-type region 58 which reaches substrate 40 to completely isolate N-type region 34. During this diffusion a layer of borosilicate glass forms over the surface of the wafer. An annular aperture is etched in the masking layer and a second boron diffusion performed to form P-type top gate region 31 which defines the channel 33, the circular drain 30 and the annular source 32. Phosphorous is diffused into the drain and source regions to form N+ type enhancement regions 35, 36. The thin layer of phosphosilicate glass that forms is removed by etching, an annular region of masking layer 48 is removed over gate region 31, and the oxide layer is removed from the lower face of the wafer Fig. 4J (not shown). A layer of aluminium is evaporated on to the top surface and etched to form drain, top gate, and source contacts 25, 26, 27, and a layer of gold 44 is deposited on the lower face of the wafer. A plurality of devices may be produced simultaneously in the same wafer which is then cut into individual dice which are encapsulated by soldering layer 44 to a metal header 14, Fig. 1 (not shown), and thermocompression bonding fine wires to the contacts 26, 27, 25 and to the ends of lead-out wires 16, 17, 18. Wire 16, which is connected by fine wire 21 to the top gate contact 26 is also connected by fine wire 23 to header 14 which makes contact with region 40 part of which operates as the lower gate. The encapsulation is completed by welding cap 11 to header 14. The device is tested and classified according to its parameters. The device may be produced as part of a monolithic integrated circuit. Complementary devices may also be produced, but in these N+ type enhancement regions are unnecessary since the impurity concentration of the gate is sufficiently high for it to be unaffected by the aluminium contact. |
