发明名称 |
Semiconductor memory device without decreasing performance thereof even if refresh operation or word line changing operation occur during burst operation |
摘要 |
<p>A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete. <IMAGE></p> |
申请公布号 |
EP1600980(B1) |
申请公布日期 |
2015.02.25 |
申请号 |
EP20040027746 |
申请日期 |
2004.11.23 |
申请人 |
FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
HARA, KOTA;YAMADA, SHINICHI |
分类号 |
G11C11/406;G11C11/407;G11C7/10;G11C7/20;G11C11/4072;G11C11/409 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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