发明名称 Decoding circuit and method for improved performance and lower error floors of block-wise concatenated BCH codes with cyclic shift of constituent BCH codes
摘要 <p>A decoding method of the present invention includes the steps of: reading the coded data according to the block-unit concatenation BCH encoding method from a non-volatile memory and conducting a hard-decision decoding operation for the read data; extracting a message block including an error in response to a hard-decision decoding failure; acquiring a first index which is the index of a row code word corresponding to the message block including the error and a second index which is the index of a column code word; calculating the respective polynomials of the code words failed to be decoded based on the first and second indexes; and correcting the errors using the calculated polynomials.</p>
申请公布号 KR101496052(B1) 申请公布日期 2015.02.25
申请号 KR20130146324 申请日期 2013.11.28
申请人 发明人
分类号 G06F11/10 主分类号 G06F11/10
代理机构 代理人
主权项
地址