Memory access control in a memory device

摘要

A memory device 20 comprising an array of bitcells 22 arranged as a plurality of rows and columns of bitcells having a plurality of wordlines WL_L, WL_R and a plurality of readout channels 28 which may comprise a read signal sense amplifier (SA). A control unit CTRL is configured to control access to the array of bitcells 22, wherein in response to a memory access request specifying a memory address the control unit CTRL is configured to activate a selected wordline WL_R, WL_L and to activate the plurality of readout channels 28 , and to access a row of bitcells in the array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal (LREN) and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline (114, 116 figure 4) and a portion of the plurality of readout channels, such that only a portion of the data word is accessed. The wordline may comprise two partial wordlines (sub-wordlines) each associated with a left and right side system operation (see figure 2), having control lines WL_L, WL_R , SAE_L and SAE_R separately enabled and controlled by means of the combinatorial logic disclosed in figure 3 comprising AND gates. Activation of a partial wordline may be dependent on a wordline clock signal (CLK, GTP, figure 2)) to generate a first and second wordline clock signal made inactive by a masking signal (LREN). The memory device may be a system on chip (SOC). In an embodiment the partial selection of a 64 bit data word (50% system selection) allows for the saving of significant power consumption due to reduction in static DC currents and dynamic (clock determined) currents. A claim to a memory system compiler is also included.