| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To cancel an offset voltage of a fully differential operational amplifier and an output offset voltage due to a relative variation in the resistance value of resistors. <P>SOLUTION: An output offset voltage cancellation circuit 109 is configured to apply a voltage for gradually bringing an output offset voltage of a fully differential operational amplifier 1 toward zero to an input stage of the fully differential operational amplifier 1 in accordance with the polarity of the output offset voltage from a circuit start time. A control logic circuit 113 is adapted to instruct a switch circuit 115 to connect a first feedback resistor 23 between an inverting input terminal and a positive output terminal of the fully differential operational amplifier 1 and a second feedback resistor 24 between a non-inverting input terminal and a negative output terminal of the fully differential operational amplifier 1 during an output offset voltage cancellation period from the circuit start to when the output offset voltage of the fully differential operational amplifier 1 becomes zero. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
