| 摘要 |
Disclosed is a germanium barrier embedded in a MOS device. An integrated circuit structure comprises, a gate stack on a semiconductor substrate and an opening which is extended toward the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium area is in the opening, wherein the first silicon germanium area has a first germanium percentage. A second silicon germanium area is on the first silicon germanium area, wherein the second silicon germanium area has a second germanium percentage higher than the first germanium percentage. A third silicon germanium area is on the second silicon germanium area, wherein the third silicon germanium area has a third germanium percentage lower than the second germanium percentage. |
