Semiconductor timing improvement

摘要

Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.

主权项

1. A method implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to:
set starting across chip variation assumptions using design rules; design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design; place a predetermined number of devices spanning from one side of the test chip and/or product chip to another side of the test chip and/or product chip in one or more configurations; measure a performance of each of the devices to obtain an understanding of how the devices are performing across the test chip and/or product chip; map the performance of each of the devices to corresponding regions of the test chip and/or product chip; establish a relationship between the measured performance of each device and each corresponding region of the test chip and/or product chip to generate performance gradients across the test chip and/or product chip that summarize affects of process variation and process level densities on performance of circuits within the test chip and/or product chip: compare the generated performance gradients across the test chip and/or the product chip to the starting across chip variation assumptions to determine whether the starting across chip variation assumptions present a pessimistic or optimistic guard band; and adjust the starting across chip variation assumptions based on the comparison between the generated performance gradients and the starting across chip variation assumptions such that adjusted across chip variation assumptions present a more precise guard band, wherein at least the step of designing the test chip and/or the product chip is performed using a processor of the computer infrastructure.