| 发明名称 | On-chip memory (OCM) physical bank parallelism | ||
| 摘要 | According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle. | ||
| 申请公布号 | US8966152(B2) | 申请公布日期 | 2015.02.24 |
| 申请号 | US201213565736 | 申请日期 | 2012.08.02 |
| 申请人 | Cavium, Inc. | 发明人 | Bouchard Gregg A.;Goyal Rajan;Pangborn Jeffrey A.;Ansari Najeeb I. |
| 分类号 | G06F12/00;G06F9/46;G06F13/16;G06F12/08;G06F12/02;G06F12/04;G06N5/02;H04L12/26;H04L29/06;H04L12/747;H04L12/851;H04L12/801;H04L12/741;G06F9/50;H04L29/08 | 主分类号 | G06F12/00 |
| 代理机构 | Hamilton, Brook, Smith & Reynolds, P.C. | 代理人 | Hamilton, Brook, Smith & Reynolds, P.C. |
| 主权项 | 1. An integrated on-chip memory device component, comprising: a plurality of memory banks; and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks for multiple independent data access requests, wherein each data access request includes a memory address with a first set of bits indicative of a memory bank, among the plurality of memory banks, and a second set of bits indicative of a memory row within the memory bank indicated by the first set of bits, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle. | ||
| 地址 | San Jose CA US | ||