Methods for operating SRAM cells

摘要

A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.

主权项

1. A method comprising:
performing a first operation on a Static Random Access Memory (SRAM) array by supplying a Vss voltage to a CVss line of the SRAM array, wherein the SRAM array comprises a plurality of rows and a plurality of columns of SRAM cells, each comprising:
a p-well region;a first and a second n-well region on opposite sides of the p-well region; anda first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively, wherein the first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs; and performing a second operation on the SRAM array by supplying a modified Vss voltage to the CVss line, wherein the Vss voltage and the modified Vss voltage are different from each other, and wherein during the first operation and the second operation, voltages of the p-well region are different from the Vss voltage and the modified Vss voltage, respectively.