| 发明名称 |
Reduction of jitter in an integrated circuit |
| 摘要 |
Reducing jitter in a circuit design includes selecting a plurality of circuit elements of a circuit design clocked using a first clock signal and assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion. The circuit elements assigned to a first group of the plurality of groups are clocked using the first clock signal. The circuit elements assigned to a second group of the plurality of groups are clocked using a second clock signal different from the first clock signal. |
| 申请公布号 |
US8966432(B1) |
申请公布日期 |
2015.02.24 |
| 申请号 |
US201314019897 |
申请日期 |
2013.09.06 |
| 申请人 |
Xilinx, Inc. |
发明人 |
Klein Matthew H. |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
Cuenot Kevin T. |
| 主权项 |
1. A method of reducing jitter in a circuit design, the method comprising:
selecting a plurality of circuit elements of a circuit design clocked using a first clock signal; assigning, using a processor, the plurality of circuit elements to different ones of a plurality of groups according to a balancing criterion; clocking the circuit elements assigned to a first group of the plurality of groups using the first clock signal; and clocking the circuit elements assigned to a second group of the plurality of groups using a second clock signal different from the first clock signal. |
| 地址 |
San Jose CA US |
