Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor

摘要

A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.

主权项

1. A nonvolatile semiconductor memory device, comprising:
a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; a first latch circuit for controlling a voltage that is supplied to the drain during a program operation; a second latch circuit that holds data read out from the P-type memory cell transistor; and a control circuit which executes a read disturb determination sequence of exercising control so as to latch, in the second latch circuit, first data read out by applying a first voltage to the gate of the P-type memory cell transistor, generate recovery data by taking logic of the first data and second data read out by applying a second voltage to the gate of the P-type memory cell transistor, and latch the recovery data in the first latch circuit.