发明名称 |
Method of fabricating semiconductor devices |
摘要 |
A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern. |
申请公布号 |
US8962422(B2) |
申请公布日期 |
2015.02.24 |
申请号 |
US201313804398 |
申请日期 |
2013.03.14 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Seong Ho-Jun;Sim Jae-Hwang |
分类号 |
H01L27/088;H01L29/66;H01L21/28;H01L29/788;H01L27/115;H01L49/02;H01L27/06 |
主分类号 |
H01L27/088 |
代理机构 |
Lee & Morse, P.C. |
代理人 |
Lee & Morse, P.C. |
主权项 |
1. A method of fabricating a semiconductor device, the method comprising:
etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern; filling a field insulating material in the field trench to form a field region; forming an upper gate pattern on the lower gate pattern; sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern; forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern; forming an interlayer insulating layer covering the first and second resistive patterns; and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern. |
地址 |
Suwon-si, Gyeonggi-do KR |