| 摘要 |
<p>The present invention relates to a data recovery circuit and, more specifically, to a data recovery circuit capable of minimizing the number of clocks used in a data recovery operation. The data recovery circuit includes: a data sampling unit configured to receive source data including data to be restored and edge data and to sample the source data by using data clocks and an edge clock; a data extracting unit configured to extract the data to be restored and the edge data from the data sampled by the data sampling unit; a control signal generating unit configured to generate a phase control signal for controlling phases of the data clock and the edge clock in response to the edge data; and a multi-clock control unit configured to control the phases of the data clock and the edge clock in response to the phase control signal.</p> |
