Digital architecture using one-time programmable (OTP) memory

摘要

In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.

主权项

1. An apparatus comprising:
a digital signal processor (DSP); a controller coupled to the DSP to provide control signals to the DSP; a one-time programmable (OTP) memory coupled to the DSP and the controller, the OTP memory including firmware having a first code block to control the DSP and a second code block to control the controller; a plurality of volatile memories including a first program volatile memory to store the first code block and a first data volatile memory associated with the DSP and a second program volatile memory to store the second code block and a second data volatile memory associated with the controller; and a memory controller coupled to the OTP memory and the plurality of volatile memories, wherein the apparatus is a first radio tuner formed from a first semiconductor die of a wafer, and wherein a second radio tuner formed from a second semiconductor die of the wafer includes a different firmware version, the first and second radio tuners fabricated from a single mask set.