Phase-locked loop circuit

摘要

A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO.

主权项

1. A phase-locked loop (PLL) circuit comprising:
a phase frequency detector, being configured to generate a correction signal according to a reference signal and a feedback signal; a first charge pump (CP), being configured to generate a first current according to the correction signal; a first loop component set, being configured to generate a first offset current, and generate a first control voltage according to the first current and the first offset current; a second CP, being configured to generate a second current according to the correction signal; a second loop component set, being configured to generate a second offset current and a direct current (DC) adjustment voltage, and generate a second control voltage according to the second current, the second offset current and the DC adjustment voltage; a voltage control oscillator (VCO), being configured to generate an oscillation signal according to the first control voltage and the second control voltage; and a frequency divider, being configured to divide the oscillation signal to generate the feedback signal.