Information processing apparatus and information processing method

摘要

There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an access request to the DRAM, the bus master comprises a transmission unit configured to transmit, to the memory controller, using a signal indicating a type of burst access which is requested of the memory controller by the bus master, an instruction to designate that an auto-precharge operation is not to be performed after accessing the first address, and an instruction to designate that an auto-precharge operation is to be performed after accessing the first address.

主权项

1. A memory controlling system comprising:
a plurality of information processing apparatuses connected to a memory controller; a memory; and the memory controller, which accesses the memory, wherein at least one of the plurality of information processing apparatuses comprises: a specifying unit configured to specify a first address and a second address on the memory to be sequentially accessed by the information processing apparatus via the memory controller; a determining unit configured to determine whether the first and second addresses are corresponding to the same page on the memory; and an outputting unit configured to output, to the memory controller: address information corresponding to the first and second addresses with a control signal indicating that an exclusive access to a bus which connects the plurality of information processing apparatuses and the memory controller is not requested, in a case where the determining unit determines that the first and second addresses are not corresponding to the same page on the memory, and address information corresponding to the first and second addresses with a control signal indicating that the exclusive access to the bus is requested, in a case where the determining unit determines that the first and second addresses are corresponding to the same page on the memory, and the memory controller comprising: a receiving unit configured to receive the address information corresponding to the first and second addresses and the control signal output by the information processing apparatus; and a memory controlling unit configured to output to the memory: a first control command such that a page on the memory is closed according to completion of access to the first address in a case where the received control signal indicates that the exclusive access to the bus is not requested, and a second control command such that the page on the memory is not closed according to the completion of access to the first address in a case where the received control signal indicates that the exclusive access to the bus is requested.