Multi-level sigma-delta ADC with reduced quantization levels

摘要

A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

主权项

1. A multi-level sigma-delta Analog-to-Digital converter comprising:
a direct path having an input terminal to receive an input analog signal and an output terminal to provide an output digital signal corresponding to said input analog signal, said direct path comprising:
an analog integrator having an input terminal to receive a first analog signal representative of the input analog signal and an output terminal to provide a second analog signal,a first computation block arranged to receive said second analog signal and to provide a first analog computed signal;a quantizer having a respective input terminal connected to the first computation block to receive the first analog computed signal and a respective output terminal operatively connected to the output terminal of the direct path, wherein said direct path of the converter further comprises a digital integrator interposed between the output terminal of the quantizer and the output terminal of the converter, said digital integrator comprising a delay block having an input terminal to receive the output digital signal and an output terminal to provide a delayed digital signal, wherein said direct path further comprises a second computation block arranged to receive a third analog signal representative of the input analog signal and to provide a second analog computed signal, the converter further comprising a first feedback path arranged to provide to the first computation block a feedback analog signal representative of the delayed digital signal present at the output terminal of the delay block of the digital integrator, said first computation block being arranged to subtract said feedback analog signal from the second analog signal, the converter being characterized in that said feedback analog signal is injected via the first feedback path and the first computation block directly at the input terminal of the quantizer, the converter further comprising a second feedback path, wherein the second feedback path comprises a digital-to-analog converter having an input connected to the output terminal of the direct path and an output connected to second computation block, said input is used to receive the output digital signal present at the output terminal of the direct path.