发明名称 |
Clock gated delay line based on setting value |
摘要 |
In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value. |
申请公布号 |
US8963601(B1) |
申请公布日期 |
2015.02.24 |
申请号 |
US201314015601 |
申请日期 |
2013.08.30 |
申请人 |
Cavium, Inc. |
发明人 |
Balasubramanian Suresh |
分类号 |
H03H11/26;H03K3/011;H03K5/14 |
主分类号 |
H03H11/26 |
代理机构 |
Hamilton, Brook, Smith & Reynolds, P.C. |
代理人 |
Hamilton, Brook, Smith & Reynolds, P.C. |
主权项 |
1. A delay circuit comprising:
a delay line configured to receive a clock input signal, a setting value and a plurality of delay element select signals and to output a delayed clock signal based on the setting value, the delay line comprising a plurality of delay elements connected in series, each delay element configured to receive one of the plurality of delay element select signals and output a delayed signal based on the delay element select signal, wherein each delay element is a multiplexer having a first input configured to receive an input signal corresponding to the outputs of the delay element preceding in the series, a second input connected to ground and a multiplexer select input connected to the corresponding delay element select signal. |
地址 |
San Jose CA US |