Impedance circuit and method for signal transformation

摘要

An impedance circuit includes an input terminal, a first and a second capacitive arrangement and an output terminal coupled to the input terminal by a network. The network includes the first and the second capacitive arrangement. The first capacitive arrangement includes a varactor circuit having a varactor and at least one series circuit. The at least one series circuit includes a capacitor and a switch in series connection and is coupled parallel to the varactor circuit. The second capacitive arrangement comprises an additional capacitor.

主权项

1. An impedance circuit, comprising:
an input terminal; a first capacitive arrangement that comprises a varactor circuit having a varactor and a series circuit that comprises a capacitor and a switch in series connection, the series circuit coupled in parallel with the varactor circuit; a second capacitive arrangement that comprises an additional capacitor; and an output terminal coupled to the input terminal by a network that comprises the first capacitive arrangement and the second capacitive arrangement; and a control circuit that controls the switch of the series circuit and controls the varactor circuit and comprising an input for receiving a control signal and an analog-to-digital converter coupled between the input of the control circuit and a control terminal of the switch of the series circuit, wherein the analog-to-digital converter is realized as a pipe-line converter and comprises a first sub-circuit with a first comparator and a first subtraction unit and also comprises a second sub-circuit with a second comparator and a second subtraction unit such that output terminals of the first and the second comparators form an output of the analog-to-digital converter and wherein the analog-to-digital converter incorporates a generator such that an output of the second subtraction unit is connected to an output of the generator and the generator provides a generator signal that depends on a difference between the predetermined capacitance value of the first capacitive arrangement and the present capacitance value of the series circuit.