| 发明名称 | Error detecting circuit and semiconductor apparatus including the same | ||
| 摘要 | An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other. | ||
| 申请公布号 | US8966326(B2) | 申请公布日期 | 2015.02.24 |
| 申请号 | US201313772187 | 申请日期 | 2013.02.20 |
| 申请人 | SK Hynix Inc. | 发明人 | Lee Kang Youl;Park Mun Phil |
| 分类号 | G06F11/00;G11C29/42;G11C29/04 | 主分类号 | G06F11/00 |
| 代理机构 | William Park & Associates Patent Ltd. | 代理人 | William Park & Associates Patent Ltd. |
| 主权项 | 1. An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, but levels of the 2-bit first test data signals are different from levels of the 2-bit second test data signals. | ||
| 地址 | Gyeonggi-do KR | ||