发明名称 |
Data processing system operable in single and multi-thread modes and having multiple caches and method of operation |
摘要 |
In some embodiments, a data processing system includes a processing unit, a first load/store unit LSU and a second LSU configured to operate independently of the first LSU in single and multi-thread modes. A first store buffer is coupled to the first and second LSUs, and a second store buffer is coupled to the first and second LSUs. The first store buffer is used to execute a first thread in multi-thread mode. The second store buffer is used to execute a second thread in multi-thread mode. The first and second store buffers are used when executing a single thread in single thread mode. |
申请公布号 |
US8966232(B2) |
申请公布日期 |
2015.02.24 |
申请号 |
US201213370420 |
申请日期 |
2012.02.10 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Tran Thang M. |
分类号 |
G06F9/30;G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A data processing system comprising:
a processing unit including:
a first LSU (load/store unit);a second LSU configured to operate independently of the first LSU in single and multi-thread modes;a first store buffer coupled to the first and second LSUs; anda second store buffer coupled to the first and second LSUs, wherein
the first store buffer is used to execute a first thread in multi-thread mode,the second store buffer is used to execute a second thread in multi-thread mode, andthe first and second store buffers are used when executing a single thread in single thread mode. |
地址 |
Austin TX US |