| 摘要 |
PROBLEM TO BE SOLVED: To implement such calibration of a sample-and-hold circuit as provides lower noise and higher analog-digital conversion accuracy.SOLUTION: In a pipelined A/D converter 1 including an MDAC (multiplying DA converter), Gain-AMP included in the MDAC using SPM comprises MOS transistors as a differential pair having output ends connected to a sampling capacitor of a subsequent stage, MOS transistors as load sections connected to the differential pair, a current source for supplying a current to the MOS transistors as the differential pair, and current sources for regulating currents flowing through MOS transistors as the load sections. An output Vout resulting from digital conversion of an input signal Vin in the pipelined A/D converter 1 is multiplied by a random variable PN, a multiplication result is integrated as an error signal Verr, and a gain of Gain-AMP is adjusted on the basis of the integrated error signal Verr. |
