发明名称 SEMICONDUCTOR MEMORY APPARATUS
摘要 The present invention provides a semiconductor memory apparatus capable of improving operating efficiency of pipes by adjusting the pulse of an output control signal for the pipes and latching an output of the pipes, a data output method thereof. A semiconductor memory apparatus includes an output control signal generator, a plurality of pipes, and a latch unit. The output control signal generator generates a first output control signal and a second output control signal in response to a read command and latency. The pipes output data transmitted through data lines in response to the first and second output control signals. The latch unit latches an output of the pipes.
申请公布号 KR20150018098(A) 申请公布日期 2015.02.23
申请号 KR20130094577 申请日期 2013.08.09
申请人 发明人
分类号 G11C7/10;G11C11/4093;G11C11/4096 主分类号 G11C7/10
代理机构 代理人
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