| 摘要 |
PROBLEM TO BE SOLVED: To provide an arithmetic processor capable of improving throughput at a time of issuing two instructions.SOLUTION: An arithmetic processor includes: a first instruction execution unit that executes a first instruction by a pipeline operation that needs only a single clock for data transition among a plurality of first staging latches including a staging latch at the last stage among a plurality of staging latches, and a multi-cycle operation that needs a plurality of clocks for data transition among a plurality of second staging latches located in front of the first staging latches among the plurality of staging latches; a second instruction execution unit that executes a second instruction; and an instruction control unit to which the first instruction and the second instruction are input, and that issues the first instruction to the first instruction execution unit and issues the second instruction to the second instruction execution unit so that execution of the first instruction overlaps execution of the second instruction. |
