PROCESSOR AND CONTROL METHOD OF PROCESSOR

摘要

When a primary cache controller of a core unit arbitrates and issues a non-cache write request in a thread “0” (zero) and a non-cache read request in a thread 1 from an instruction controller, and when the non-cache requests being arbitration objects are in issuable states by obtaining a response for a preceding non-cache write request after an issuance of the preceding non-cache write request in the thread-0 (zero) which precedes to the non-cache write request in the thread-0 (zero) being the arbitration object, the non-cache read request in the thread-1 is given priority to be issued so that the non-cache read request whose priority is low is not continued to be waited.

主权项

1. A processor, comprising:
an instruction control unit which outputs a first non-cache request belonging to a first thread from among plural threads and performing an access without holding an access object data at a cache memory, and a second non-cache request belonging to a second thread from among the plural threads and whose priority is lower than the first non-cache request; and an issuance control unit which issues the second non-cache request prior to the first non-cache request when the first non-cache request and the second non-cache request output from the instruction control unit are arbitrated to be issued, and when the first non-cache request and the second non-cache request being arbitration objects are in issuable states by obtaining a response for an issued preceding non-cache request after the preceding non-cache request in the first thread preceding to the first non-cache request is issued.