INTERFACE APPARATUS AND MEMORY BUS SYSTEM

摘要

An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

主权项

1. An interface apparatus which connects together an initiator that is arranged on an integrated circuit and a bus network that has been formed on the integrated circuit,
wherein the bus network is a packet exchange type network, and is designed so that if request data specifying a deadline time has been submitted by the initiator for a node on the bus network, response data to be issued by the node in response to the request data is received by the initiator by the deadline time, and the interface apparatus comprises: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted by the initiator, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.