Power Source for Clock Distribution Network

摘要

A clock distribution network having a separate power supply for top levels thereof is disclosed. In one embodiment, an integrated circuit includes a clock distribution network configured to distribute a clock signal to each of a number of clock consumers. The clock distribution network is arranged in a hierarchy of levels, with each of the levels including at least one buffer, and with the upper levels being closer to a source of the clock signal and the lower levels being closer to the clock consumers. The buffers of the upper levels are coupled to receive power from a first power source, via a first power grid. The buffers of the lower levels are coupled to receive power from a second power source, separate from the first, via a second power grid.

主权项

1. An integrated circuit comprising:
a clock source configured to generate a clock signal; and a clock distribution network configured to distribute the clock signal, wherein the clock distribution network includes a plurality of levels divided into a first subset and a second subset, wherein each of the plurality of levels includes one or more buffers, wherein each of the buffers of the first subset is coupled to receive power via a first power grid and wherein each of the buffers of the second subset is coupled to receive power via a second power grid that is separate and distinct from the first power grid.