| 主权项 |
1. A microprocessor circuit comprising:
a software programmable microprocessor core, a data memory accessible via a data memory bus, the data memory comprising a plurality of sets of configuration data structured in accordance with respective predetermined data structure specifications for a plurality of configurable math hardware accelerators, the data memory further comprising respective sets of input data for the plurality of configurable math hardware accelerators, each of the configurable math hardware accelerators being configured to apply a predetermined signal processing function to the set of input data in accordance with a received set of the register level configuration data, a configuration controller coupled to the data memory via the data memory bus and to the plurality of configurable math hardware accelerators, said configuration controller being configured to: fetching the set of configuration data for each math hardware accelerator from a predetermined address space of the data memory through the data memory bus, translating the plurality of sets of configuration data to respective sets of register level configuration data for the plurality of configurable math hardware accelerators in accordance with the respective predetermined data structure specifications, transmitting each set of register level configuration data to the corresponding configurable math hardware accelerator, writing each set of the register level configuration data to one or more configuration registers of the corresponding configurable math hardware accelerator. |
