发明名称 CACHE MEMORY CONTROL PROGRAM, PROCESSOR INCORPORATING CACHE MEMORY, AND CACHE MEMORY CONTROL METHOD
摘要 A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area.
申请公布号 US2015052314(A1) 申请公布日期 2015.02.19
申请号 US201414458424 申请日期 2014.08.13
申请人 FUJITSU LIMITED 发明人 FUJII Masatoshi;HINOHARA Hisashi;YUBA Yasuhiro
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
代理机构 代理人
主权项 1. A non-transitory processor-readable storage medium storing a cache memory control program which causes a processor to execute a procedure, comprising: cache area allocating including allocating, in response to an acquisition request which is issued during execution of a process by the processor and requests an allocation of a dedicated cache area in a cache memory, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated with respect to object processing, which is an object for the acquisition request, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area, and wherein a memory access command that is issued during the object processing to which the dedicated cache area is allocated is executed by the processor by using the dedicated cache area which is allocated.
地址 Kawasaki-shi JP