Passivation for Group III-V Semiconductor Devices Having a Plated Metal Layer over an Interlayer Dielectric Layer

摘要

A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

主权项

1. A semiconductor device, comprising:
a Group III-V semiconductor substrate; a first metal layer over the substrate; a planarizing interlayer dielectric layer over the first metal layer, the interlayer dielectric layer defining a via extending therethrough to the first metal layer; a second metal layer, greater in thickness than the first metal layer, over the interlayer dielectric layer, the second metal layer comprising an interconnect extending through the via into contact with the first metal layer, the second metal layer patterned to define at least one conductor; and a passivation layer over the second metal layer and the interlayer dielectric layer, the passivation layer comprising stacked regions of dielectric material, ones of regions under tensile stress alternating with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.