CONTROL CIRCUIT FOR FRAME MEMORY, DISPLAY DEVICE INCLUDING THE SAME AND METHOD OF CONTROLLING THE SAME

摘要

A control circuit for a frame memory includes a divider, a frame memory, a read control circuit, and a write control circuit. The divider divides image data into subfield data according to a plurality of subfields, where the image data is provided in synchronization with a first synchronization signal and in a unit of a frame. The frame memory has a plurality of blocks to store the subfield data. The read control circuit sequentially reads the subfield data from the blocks in synchronization with a second synchronization signal. The write control circuit writes new data to a first block before data written in a second block is read, and after data written in the first block is read by the read control circuit. The second synchronization signal may have a same cycle as the first synchronization signal and may be delayed by a preset delay time.

主权项

1. A control circuit for a frame memory, comprising:
a division circuit to divide image data into a plurality of subfield data according to a plurality of subfields, the image data to be provided in synchronization with a first synchronization signal and in a unit of a frame; a frame memory having a plurality of blocks to which the subfield data is to be written; a read control circuit to sequentially read the subfield data from the blocks in synchronization with a second synchronization signal, the second synchronization signal having substantially a same cycle as the first synchronization signal and delayed by a preset delay time; and a write control circuit to write new data to a first block among the plurality of blocks before data written in a second block among the plurality of blocks is read, and after data written in the first block is read by the read control circuit.