TRANSCEIVER WITH WAKE UP DETECTION

摘要

A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.

主权项

1. A transceiver with wake up detection includes:
a primary control unit used for transmitting a first transmission signal, a second transmission signal, a first idle signal and a second idle signal; a transmission unit electrically connected to the primary control unit and having a first logic set, a second logic set, a third logic set, a first loop and a second loop, the first logic set comprises a first logic gate and a second logic gate, the second logic set comprises a third logic gate and a fourth logic gate, the third logic set comprises a fifth logic gate and a sixth logic gate electrically connected to the fifth logic gate, the first loop comprises a first transistor electrically connected to the first logic gate and a second transistor electrically connected to the fourth logic gate, the second loop comprises a third transistor electrically connected to the third logic gate and a fourth transistor electrically connected to the second logic gate, the first transistor electrically connects to the fourth transistor, the second transistor electrically connects to the third transistor, the fifth logic gate receives the first idle signal and the second idle signal and outputs a first enabling signal, the sixth logic gate outputs a second enabling signal, the first logic gate and the third logic gate receive the second enabling signal, the second logic gate and the fourth logic gate receive the first enabling signal, the first logic set receives the first transmission signal, the second logic set receives the second transmission signal, the first loop outputs a first differential signal, the second loop outputs a second differential signal; and a receiving unit electrically connected to the primary control unit and the transmission unit and having a wake up detection circuit, the wake up detection circuit comprises a first comparator, a second comparator and a fourth logic set electrically connected to the first comparator and the second comparator, when the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic gate set outputs an idle state signal and a data signal to the primary control unit to make the transceiver receiving a wake up signal and switching an operation mode of the transceiver from a low power mode to a normal mode.