发明名称 オンチップ並列処理システム及び通信方法
摘要 <p>Disclosed is an on-chip parallel processing system in which a plurality of routers and a plurality of nodes are arranged on a chip, each of the plurality of nodes belongs to any of a plurality of partitions that divide the chip into a plurality of regions, each of the plurality of nodes is connected to any one of the plurality of routers by way of a communication medium and each of the plurality of routers is connected to an adjacent router by way of the communication medium, and the plurality of routers relay packets including data that is transmitted and received in communication between the plurality of nodes. First and second communication channels are set in the communication medium. Each of the plurality of routers and each of the plurality of nodes transmit and receive packets in a first communication channel in communication between nodes belonging to the same partition, and transmit and receive packets in a second communication channel in communication between nodes belonging to mutually different partitions.</p>
申请公布号 JP5673554(B2) 申请公布日期 2015.02.18
申请号 JP20110545164 申请日期 2010.11.25
申请人 发明人
分类号 G06F15/173;G06F15/80 主分类号 G06F15/173
代理机构 代理人
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