決定帰還等化と追跡とのための単一キャリアバースト構造

摘要

Certain aspects of the present disclosure relate to a method for employing a special format for transmitting data blocks which allows parallel equalizations at a receiver. By applying parallel equalization operations, a clock at the receiver can operate at a fraction of the input signal's data rate, which is more practical in the case of very high data rates while power dissipation is also reduced.