发明名称 Digital power gating with state retention
摘要 A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.
申请公布号 EP2811653(A3) 申请公布日期 2015.02.18
申请号 EP20140166644 申请日期 2014.04.30
申请人 VIA TECHNOLOGIES, INC. 发明人 LUNDBERG, JAMES
分类号 H03K19/00;G06F1/32;H03K17/00 主分类号 H03K19/00
代理机构 代理人
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