发明名称 フィルタリング処理回路とそれを有するマッチング回路
摘要 <p><P>PROBLEM TO BE SOLVED: To perform filtering processing fast with a simple circuit configuration. <P>SOLUTION: There is provided a filtering processing circuit which extracts a minimum difference absolute value sum among difference absolute value sums corresponding to a plurality of deviation amounts between two images obtained at different viewpoints. The filtering processing circuit includes: a minimum difference absolute value sum holding circuit which holds, when a difference absolute value sum among a plurality of difference absolute value sums corresponding to the plurality of deviation amounts input to an input circuit is the minimum difference absolute value sum up to the input point of time, the difference absolute value sum as a minimum difference absolute value sum; a second minimum difference absolute value sum detection circuit which detects and holds a second minimum difference absolute value sum that is the second smallest; and a selector circuit which inputs the input difference absolute value sum to the second minimum difference absolute value sum detection circuit when the plurality of difference absolute value sums are not the minimum difference absolute value sum up to the input point of time, or inputs, to the second minimum difference absolute value sum detection circuit, the original minimum difference absolute value sum output from the minimum difference absolute value sum holding circuit following an update of the minimum difference absolute value in the minimum difference absolute value sum holding circuit when the plurality of difference absolute value sums include the minimum difference absolute value sum. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5672121(B2) 申请公布日期 2015.02.18
申请号 JP20110082428 申请日期 2011.04.04
申请人 发明人
分类号 H04N13/00;G06T1/00;G06T1/20 主分类号 H04N13/00
代理机构 代理人
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