发明名称 |
High speed phase selector with a glitchless output used in phase locked loop applications |
摘要 |
A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown. |
申请公布号 |
US8957704(B1) |
申请公布日期 |
2015.02.17 |
申请号 |
US201314020229 |
申请日期 |
2013.09.06 |
申请人 |
Synopsys, Inc. |
发明人 |
Wolfer Skye;Yokoyama-Martin David A. |
分类号 |
H03K17/00;H03K5/125 |
主分类号 |
H03K17/00 |
代理机构 |
Fenwick & West LLP |
代理人 |
Fenwick & West LLP |
主权项 |
1. A digital phase selector circuit comprising:
a plurality of clock phase inputs, each of the plurality of clock phase inputs configured to receive one of a plurality of distinct clock phases, each of the plurality of distinct clock phases alternating between a high state and a low state; a plurality of control signal inputs each configured to receive one of a plurality of control signals, each control signal selecting one of the plurality of distinct clock phases to output by the digital phase selector circuit; and a clock output configured to output a clock signal without a glitch based on the plurality of control signals; wherein the digital phase selector circuit is configured to output the clock signal without the glitch by transitioning from outputting a first clock phase from the plurality of distinct clock phases as the clock signal to outputting a second clock phase from the plurality of distinct clock phases as the clock signal when both the first clock phase and the second clock phase are in the low state. |
地址 |
Mountain View CA US |