Semiconductor device having plural semiconductor chip stacked with one another

摘要

Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.

主权项

1. A device comprising:
a plurality of external terminals including first and second external terminals; a first semiconductor chip including a plurality of control circuits that comprises a first control circuit, the first control circuit generating a first control signal; and a second semiconductor chip stacked with the first semiconductor chip, the second semiconductor chip comprising;
a first test terminal configured to be supplied with a first test signal, the first test terminal being free from connecting to any one of the external terminals;a second test terminal configured to be supplied with the first test signal, the second test terminal being coupled to the first external terminal without connecting to any one of control circuits of the first semiconductor chip;a first normal terminal configured to be supplied with the first control signal, the first normal terminal being coupled to the second external terminal with an intervention of the first control circuit of the first semiconductor chip; anda first selection circuit including first and second input nodes, the first input node being coupled in common to the first and second test terminals and the second input node being coupled to the first normal terminal.