Intelligent chassis management

摘要

A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

主权项

1. An electronic system comprising:
a first route module, the first route module having a first route processor and a first route field-programmable gate array (FPGA) that is capable of communicating with the first route processor and that receives power when the first route module is powered down, wherein the first route FPGA includes a heartbeat timer and a heartbeat counter; a plurality of removable line modules each having multiple electronic components, each including a line processor and a line FPGA that is capable of communicating with the line processor and that receives power when the second module is powered down, wherein the line FPGA in each line module controls at least some of the multiple electronic components of that line module without the involvement of the line processor; and a first point-to-point serial management bus connection dedicated between the first route FPGA and each line FPGA in each line module, wherein the first route FPGA sends control commands over each first point-to-point serial management bus connection to the line FPGAs to control the at least some of the multiple electronic components, and wherein each line FPGA is operable to push data to the first route module; wherein the first route FPGA and each line FPGA are configured to exchange heartbeat messages with each other across their first point-to-point serial management bus connection, at least some of the heartbeat message exchanges occurring without the involvement of the first route processor and without the involvement of the line processors, and wherein the first route FPGA is capable of alerting the first route processor when heartbeat message exchanges from the line FPGAs fall outside of a set of parameters set for a normal heartbeat message exchange.